The present invention relates to a timing extraction circuit for extracting a clock pulse waveform from an input pulse waveform, the circuit including a phase-locked loop with a phase comparator having a first input to which the input pulse waveform is supplied, a second input and an output which is coupled in cascade at least with a controlled oscillator the output of which is coupled to the second input of the phase comparator, the clock pulse waveform being generated at the output of the controlled oscillator.
Such a timing extraction circuit is generally known in the art, e.g. from the article "The Jitter Performance of Phase-Locked Loops Extracting Timing From Baseband Data Wave forms" by D. L. Duttweiler, published in the Bell System Technical Journal, January 1976, pp. 37-58, more particularly pp. 45-47. A drawback of this known circuit is that the correction signal representing the phase error between the clock pulse waveform and the input pulse waveform is proportional to the probability of having a transistion (a negative going or a positive-going change or excursion) in the input pulse wavform, i.e. to the pulse density of the latter waveform.